DK-DEV-5SGXEA7N【PDF 30/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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2-8

Embedded Memory Configurations

SV51003

2013.05.06

Features

Power-up state

Asynchronous clears

Write/read operation triggering

Same-port read-during-write

M20K

Output ports are

cleared.

Output registers and

output latches

Rising clock edges

Output ports set to

"new data".

MLAB

? Registered output

ports — Cleared.

? Unregistered output ports — Read

memory contents.

Output registers and output latches

Rising clock edges

Output ports set to "don't care".

Mixed-port read-during-write

Output ports set to "old Output ports set to "old data", "new

data" or "don't care".

data", "don't care", or "constrained

don't care".

ECC support

Soft IP support using

the Quartus II

Soft IP support using the Quartus II

software.

software.

Built-in support in

x32-wide simple dual-

port mode.

Related Information

Internal Memory (RAM and ROM) User Guide

Provides more information about the embedded memory features.

Embedded Memory Configurations

Table 2-6: Supported Embedded Memory Block Configurations for Stratix V Devices

This table lists the maximum configurations supported for the embedded memory blocks. The information is

applicable only to the single-port RAM and ROM modes.

Memory Block

MLAB

M20K

Depth (bits)

32

64

512

1K

2K

4K

Programmable Width

x16, x18, or x20

x8, x9, x10

x40, x32

x20, x16

x10, x8

x5, x4

Altera Corporation

8K

16K

x2

x1

Embedded Memory Blocks in Stratix V Devices

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